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🇺🇸 English README | 🇨🇳 中文文档

📖 Complete Documentation: https://wenyinwei.github.io/zlayout/

Contains API reference, tutorials, performance benchmarks, and example code.

Ultra-large scale EDA layout optimization library for advanced process nodes (2nm and below), designed to handle hundreds of millions to billions of electronic components. Built with modern C++17, featuring hierarchical spatial indexing, multi-threaded parallel processing, and advanced layout optimization algorithms.

🎯 Core Features

🚀 Ultra-Large Scale Data Processing

Intelligent Spatial Indexing: Adaptive selection among QuadTree, R-tree, Z-order and other algorithms
Hierarchical Optimization: IP block-level hierarchical layout optimization, easily handling billion-scale components
Multi-threaded Parallelism: Full utilization of multi-core CPUs with automatic load balancing for significant speedup
Memory Optimization: Advanced memory pool management supporting ultra-large scale datasets

🔧 Professional EDA Algorithms

Sharp Angle Detection: Efficient O(n) complexity sharp angle identification algorithm
Narrow Spacing Detection: Optimized geometric algorithms supporting design rule checking
Edge Intersection Detection: Spatial index acceleration from O(n²) to O(n log n) complexity
Layout Optimization: Multiple strategies including simulated annealing, force-directed, and timing-driven optimization

💡 Intelligent Design

Automatic Algorithm Selection: Automatically selects optimal algorithms based on data characteristics and problem scale
Multi-objective Optimization: Balanced optimization of area, timing, power, and manufacturing constraints
Process Adaptation: Support for 2nm and below advanced process design rules

🚀 Quick Start

System Requirements

Compiler: GCC 9+, Clang 8+, MSVC 2019+
C++ Standard: C++17 or higher
Build System: XMake 2.6+
Optional: OpenMP (parallel processing)

One-Click Installation

# Clone repository
git clone https://github.com/your-username/zlayout.git
cd zlayout
 
# Configure and build (enable all optimizations)
xmake config --mode=release --openmp=y
xmake build
 
# Run examples
xmake run basic_usage

Python Quick Experience

import zlayout
 
# Create layout processor
world_bounds = zlayout.Rectangle(0, 0, 1000, 1000)
processor = zlayout.GeometryProcessor(world_bounds)
 
# Add components
alu = zlayout.Rectangle(100, 100, 200, 150)
cache = zlayout.Rectangle(350, 100, 300, 200)
processor.add_component(alu)
processor.add_component(cache)
 
# Intelligent analysis
results = processor.analyze_layout(
    sharp_angle_threshold=45.0,    # Detect angles smaller than 45 degrees
    narrow_distance_threshold=5.0  # Detect regions with spacing < 5 units
)
 
print(f"Detected {results['sharp_angles']['count']} sharp angles")
print(f"Detected {results['narrow_distances']['count']} narrow spacing regions")
print(f"Detected {results['intersections']['polygon_pairs']} intersecting polygon pairs")

📈 Performance Benchmarks

Test results on Intel i7-12700K:

Algorithm Type	Data Scale	Processing Time	Use Case
Sharp Angle Detection	1M polygons	234ms	Design Rule Checking
Spatial Query	10M rectangles	0.8ms	Collision Detection
Layout Optimization	50K components	12.3s	Physical Layout
Parallel Processing	1B components	95s	Ultra-large Scale Verification

💡 Real-world Application Examples

Design Rule Checking (DRC)

#include <zlayout/zlayout.hpp>
using namespace zlayout;
 
// Create advanced process design rule checker
auto drc_checker = create_drc_checker("2nm_process");
drc_checker->set_rule("min_spacing", 0.15);      // Minimum spacing 0.15μm
drc_checker->set_rule("min_width", 0.10);        // Minimum width 0.10μm
drc_checker->set_rule("sharp_angle_limit", 30.0); // Sharp angle limit 30 degrees
 
// Batch check layout
auto violations = drc_checker->check_layout(component_list);
std::cout << "Found " << violations.size() << " violations" << std::endl;

Large-scale Layout Optimization

// 20mm x 20mm large chip layout optimization
geometry::Rectangle chip_area(0, 0, 20000, 20000);
auto optimizer = OptimizerFactory::create_hierarchical_optimizer(chip_area);
 
// Create IP block hierarchy
optimizer->create_ip_block("CPU_Complex", {1000, 1000, 8000, 8000});
optimizer->create_ip_block("GPU_Array", {10000, 1000, 9000, 8000});
optimizer->create_ip_block("Memory_Subsystem", {1000, 10000, 18000, 9000});
 
// Intelligent optimization
auto result = optimizer->optimize();
std::cout << "Optimization complete, final cost: " << result.total_cost << std::endl;

Python Integration Example

# Complete EDA flow
import zlayout
 
# 1. Create design
chip = zlayout.ChipDesign("my_soc", width=5000, height=5000)
 
# 2. Add IP modules
cpu = chip.add_ip_block("ARM_A78", x=1000, y=1000, width=2000, height=2000)
gpu = chip.add_ip_block("Mali_G78", x=3500, y=1000, width=1400, height=2000)
memory = chip.add_ip_block("DDR5_PHY", x=1000, y=3500, width=3500, height=1400)
 
# 3. Set connections
chip.add_connection(cpu, gpu, "AXI_BUS", bandwidth="1TB/s")
chip.add_connection(cpu, memory, "MEM_BUS", bandwidth="800GB/s")
 
# 4. Intelligent optimization
optimization_result = chip.optimize(
    objectives=["area", "wirelength", "timing", "power"],
    constraints={"max_utilization": 0.85, "max_temp": 85}
)
 
# 5. Analyze results
chip.analyze_and_report()

🏗️ Technical Advantages

Algorithm Innovation

Adaptive Spatial Indexing: Automatically selects optimal index structure based on data distribution
Hierarchical Parallelism: IP block-level parallel optimization, breaking traditional algorithm limitations
Intelligent Prediction: Predicts optimization effectiveness based on historical data, early termination of inefficient iterations

Engineering Optimization

Zero-copy Design: Minimizes memory allocation and data copying
Cache-friendly: Optimized data layout for improved cache hit rates
NUMA-aware: Memory access optimization for multi-socket servers

🔧 Advanced Configuration

// Hardware auto-tuning
auto config = OptimizationConfig::auto_detect_optimal();
config.thread_count = std::thread::hardware_concurrency();
config.memory_limit_gb = detect_available_memory() * 0.8;
 
// Process-specific optimization
if (process_node <= 3) {  // 3nm and below
    config.precision_level = PrecisionLevel::ULTRA_HIGH;
    config.enable_3d_awareness = true;
}

📚 Learning Resources

Getting Started Tutorial: Master ZLayout in 15 minutes
API Documentation: Complete C++ and Python API reference
Algorithm Deep Dive: In-depth understanding of core algorithm principles
Performance Tuning: Performance optimization guides for different scenarios
Real Cases: Real EDA project application cases

🧪 Testing and Validation

# Basic functionality tests
xmake test
 
# Performance benchmarks
xmake run performance_benchmark
 
# Large-scale stress testing
xmake run stress_test --components=1000000000

🤝 Contributing

We welcome contributions of all kinds:

🐛 Bug Reports: Submit detailed issues when you find problems
💡 Feature Suggestions: New feature ideas and improvement suggestions
📝 Documentation Improvements: Help improve documentation and tutorials
🔧 Code Contributions: Algorithm optimization, performance improvements, new feature development

📞 Contact

Author: Wenyin WEI 魏文崟
Email: weiwy.nosp@m.16@t.nosp@m.singh.nosp@m.ua.o.nosp@m.rg.cn | wenyi.nosp@m.n@ma.nosp@m.il.us.nosp@m.tc.e.nosp@m.du.cn
Expertise: Ultra-large scale EDA algorithm optimization, High-performance computing

ZLayout - Making billion-scale component layout optimization simple and efficient! 🚀