ZLayout EDA Library v1.0.0
Advanced Electronic Design Automation Layout Library with Bilingual Documentation
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ip_blocks.hpp
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1
8
9#pragma once
10
13#include <memory>
14#include <string>
15#include <vector>
16#include <map>
17
18namespace zlayout {
19namespace components {
20
24enum class CPUArchitecture {
25 ARM_Cortex_A53, // ARM Cortex-A53 (64-bit)
26 ARM_Cortex_A72, // ARM Cortex-A72 (64-bit)
27 ARM_Cortex_A78, // ARM Cortex-A78 (64-bit)
28 ARM_Cortex_M4, // ARM Cortex-M4 (32-bit)
29 ARM_Cortex_M7, // ARM Cortex-M7 (32-bit)
30 RISC_V_RV32I, // RISC-V 32-bit Integer
31 RISC_V_RV64I, // RISC-V 64-bit Integer
32 x86_64, // x86-64 Architecture
33 Custom // Custom architecture
34};
35
39enum class MemoryHierarchy {
40 L1_Cache, // L1 Cache
41 L2_Cache, // L2 Cache
42 L3_Cache, // L3 Cache
43 Main_Memory, // Main Memory (DDR)
44 Storage // Storage (Flash/SSD)
45};
46
50enum class InterfaceType {
51 SPI, // Serial Peripheral Interface
52 I2C, // Inter-Integrated Circuit
53 UART, // Universal Asynchronous Receiver-Transmitter
54 USB, // Universal Serial Bus
55 PCIe, // PCI Express
56 Ethernet, // Ethernet
57 WiFi, // Wi-Fi
58 Bluetooth, // Bluetooth
59 CAN, // Controller Area Network
60 Custom // Custom interface
61};
62
66class ProcessorCore : public Component {
67public:
68 ProcessorCore(const std::string& name, CPUArchitecture arch, size_t core_count = 1);
69
70 // Architecture
71 CPUArchitecture getArchitecture() const { return architecture_; }
72 size_t getCoreCount() const { return core_count_; }
73
74 // Performance characteristics
75 double getMaxFrequency() const { return max_frequency_; }
76 void setMaxFrequency(double freq) { max_frequency_ = freq; }
77
78 double getCurrentFrequency() const { return current_frequency_; }
79 void setCurrentFrequency(double freq) { current_frequency_ = freq; }
80
81 // Cache configuration
82 struct CacheConfig {
83 size_t size; // bytes
84 size_t associativity; // ways
85 size_t line_size; // bytes
86 double hit_latency; // cycles
87 double miss_latency; // cycles
88 };
89
90 void setL1Config(const CacheConfig& config) { l1_config_ = config; }
91 void setL2Config(const CacheConfig& config) { l2_config_ = config; }
92 void setL3Config(const CacheConfig& config) { l3_config_ = config; }
93
94 const CacheConfig& getL1Config() const { return l1_config_; }
95 const CacheConfig& getL2Config() const { return l2_config_; }
96 const CacheConfig& getL3Config() const { return l3_config_; }
97
98 // Pipeline configuration
99 size_t getPipelineStages() const { return pipeline_stages_; }
100 void setPipelineStages(size_t stages) { pipeline_stages_ = stages; }
101
102 // Instruction set features
103 bool hasFloatingPoint() const { return has_fpu_; }
104 void setFloatingPoint(bool has_fpu) { has_fpu_ = has_fpu; }
105
106 bool hasVectorUnit() const { return has_vector_unit_; }
107 void setVectorUnit(bool has_vector) { has_vector_unit_ = has_vector; }
108
109 // Performance metrics
110 double getIPC() const { return ipc_; } // Instructions Per Cycle
111 void setIPC(double ipc) { ipc_ = ipc; }
112
113 double getDMIPS() const { return dmips_; } // Dhrystone MIPS
114 void setDMIPS(double dmips) { dmips_ = dmips; }
115
116 // Simulation
117 void simulate(double time_step) override;
118 std::string getDescription() const override;
119
120private:
121 CPUArchitecture architecture_;
122 size_t core_count_;
123 double max_frequency_; // MHz
124 double current_frequency_; // MHz
125
126 CacheConfig l1_config_;
127 CacheConfig l2_config_;
128 CacheConfig l3_config_;
129
130 size_t pipeline_stages_;
131 bool has_fpu_;
132 bool has_vector_unit_;
133
134 double ipc_; // Instructions Per Cycle
135 double dmips_; // Dhrystone MIPS
136
137 void initializeArchitecture();
138 void updatePerformanceMetrics();
139};
140
145public:
146 enum class MemoryType {
147 DDR3, // DDR3 SDRAM
148 DDR4, // DDR4 SDRAM
149 DDR5, // DDR5 SDRAM
150 LPDDR4, // Low Power DDR4
151 LPDDR5, // Low Power DDR5
152 HBM2, // High Bandwidth Memory 2
153 HBM3, // High Bandwidth Memory 3
154 GDDR6, // Graphics DDR6
155 SRAM, // Static RAM
156 Custom // Custom memory type
157 };
158
159 MemoryController(const std::string& name, MemoryType type, size_t channels = 1);
160
161 // Memory configuration
162 MemoryType getMemoryType() const { return memory_type_; }
163 size_t getChannelCount() const { return channel_count_; }
164
165 size_t getDataWidth() const { return data_width_; }
166 void setDataWidth(size_t width) { data_width_ = width; }
167
168 double getFrequency() const { return frequency_; }
169 void setFrequency(double freq) { frequency_ = freq; }
170
171 // Capacity
172 size_t getCapacityPerChannel() const { return capacity_per_channel_; }
173 void setCapacityPerChannel(size_t capacity) { capacity_per_channel_ = capacity; }
174
175 size_t getTotalCapacity() const { return capacity_per_channel_ * channel_count_; }
176
177 // Timing parameters
179 double tCL; // CAS Latency
180 double tRCD; // RAS to CAS Delay
181 double tRP; // Row Precharge time
182 double tRAS; // Row Active time
183 double tRC; // Row Cycle time
184 double tWR; // Write Recovery time
185 double tRFC; // Refresh Cycle time
186 };
187
188 void setTimingParams(const TimingParams& params) { timing_params_ = params; }
189 const TimingParams& getTimingParams() const { return timing_params_; }
190
191 // Performance metrics
192 double getBandwidth() const; // GB/s
193 double getLatency() const; // ns
194 double getPowerConsumption() const; // W
195
196 // Simulation
197 void simulate(double time_step) override;
198 std::string getDescription() const override;
199
200private:
201 MemoryType memory_type_;
202 size_t channel_count_;
203 size_t data_width_; // bits
204 double frequency_; // MHz
205 size_t capacity_per_channel_; // bytes
206
207 TimingParams timing_params_;
208
209 void initializeMemoryType();
210 void calculatePerformanceMetrics();
211};
212
216class GPUCore : public Component {
217public:
218 enum class GPUArchitecture {
219 Mali_G78, // ARM Mali-G78
220 Mali_G710, // ARM Mali-G710
221 Adreno_640, // Qualcomm Adreno 640
222 Adreno_730, // Qualcomm Adreno 730
223 PowerVR_GT7600, // Imagination PowerVR GT7600
224 RDNA2, // AMD RDNA2
225 Ampere, // NVIDIA Ampere
226 Custom // Custom GPU
227 };
228
229 GPUCore(const std::string& name, GPUArchitecture arch, size_t compute_units = 8);
230
231 // Architecture
232 GPUArchitecture getArchitecture() const { return architecture_; }
233 size_t getComputeUnits() const { return compute_units_; }
234
235 // Performance characteristics
236 double getMaxFrequency() const { return max_frequency_; }
237 void setMaxFrequency(double freq) { max_frequency_ = freq; }
238
239 size_t getShaderCores() const { return shader_cores_; }
240 void setShaderCores(size_t cores) { shader_cores_ = cores; }
241
242 // Memory interface
243 size_t getMemoryBusWidth() const { return memory_bus_width_; }
244 void setMemoryBusWidth(size_t width) { memory_bus_width_ = width; }
245
246 double getMemoryBandwidth() const { return memory_bandwidth_; }
247 void setMemoryBandwidth(double bandwidth) { memory_bandwidth_ = bandwidth; }
248
249 // Performance metrics
250 double getGFLOPS() const { return gflops_; }
251 void setGFLOPS(double gflops) { gflops_ = gflops; }
252
253 double getTexelFillRate() const { return texel_fill_rate_; }
254 void setTexelFillRate(double rate) { texel_fill_rate_ = rate; }
255
256 // Simulation
257 void simulate(double time_step) override;
258 std::string getDescription() const override;
259
260private:
261 GPUArchitecture architecture_;
262 size_t compute_units_;
263 double max_frequency_; // MHz
264 size_t shader_cores_;
265 size_t memory_bus_width_; // bits
266 double memory_bandwidth_; // GB/s
267 double gflops_; // GFLOPS
268 double texel_fill_rate_; // Gtexel/s
269
270 void initializeArchitecture();
271};
272
276class DSPCore : public Component {
277public:
278 enum class DSPArchitecture {
279 TI_C6000, // Texas Instruments C6000
280 TI_C7000, // Texas Instruments C7000
281 Qualcomm_Hexagon, // Qualcomm Hexagon
282 Cadence_Tensilica, // Cadence Tensilica
283 Custom // Custom DSP
284 };
285
286 DSPCore(const std::string& name, DSPArchitecture arch);
287
288 // Architecture
289 DSPArchitecture getArchitecture() const { return architecture_; }
290
291 // Performance
292 double getMaxFrequency() const { return max_frequency_; }
293 void setMaxFrequency(double freq) { max_frequency_ = freq; }
294
295 size_t getMACUnits() const { return mac_units_; }
296 void setMACUnits(size_t units) { mac_units_ = units; }
297
298 // Specialized units
299 bool hasFFTUnit() const { return has_fft_unit_; }
300 void setFFTUnit(bool has_fft) { has_fft_unit_ = has_fft; }
301
302 bool hasViterbiUnit() const { return has_viterbi_unit_; }
303 void setViterbiUnit(bool has_viterbi) { has_viterbi_unit_ = has_viterbi; }
304
305 // Performance metrics
306 double getGMACS() const { return gmacs_; } // Giga MAC/s
307 void setGMACS(double gmacs) { gmacs_ = gmacs; }
308
309 // Simulation
310 void simulate(double time_step) override;
311 std::string getDescription() const override;
312
313private:
314 DSPArchitecture architecture_;
315 double max_frequency_; // MHz
316 size_t mac_units_; // Multiply-Accumulate units
317 bool has_fft_unit_;
318 bool has_viterbi_unit_;
319 double gmacs_; // Giga MAC/s
320
321 void initializeArchitecture();
322};
323
328public:
329 CommunicationInterface(const std::string& name, InterfaceType type);
330
331 // Interface type
332 InterfaceType getInterfaceType() const { return interface_type_; }
333
334 // Common parameters
335 double getMaxDataRate() const { return max_data_rate_; }
336 void setMaxDataRate(double rate) { max_data_rate_ = rate; }
337
338 double getCurrentDataRate() const { return current_data_rate_; }
339 void setCurrentDataRate(double rate) { current_data_rate_ = rate; }
340
341 // Protocol specific parameters
342 void setProtocolParameter(const std::string& param, const std::string& value);
343 std::string getProtocolParameter(const std::string& param) const;
344
345 // Connection status
346 bool isConnected() const { return is_connected_; }
347 void setConnected(bool connected) { is_connected_ = connected; }
348
349 // Simulation
350 void simulate(double time_step) override;
351 std::string getDescription() const override;
352
353private:
354 InterfaceType interface_type_;
355 double max_data_rate_; // Mbps
356 double current_data_rate_; // Mbps
357 bool is_connected_;
358
359 std::map<std::string, std::string> protocol_params_;
360
361 void initializeInterface();
362};
363
368public:
369 enum class PowerState {
370 Active, // Full power
371 Idle, // Low power idle
372 Standby, // Standby mode
373 Sleep, // Sleep mode
374 DeepSleep, // Deep sleep mode
375 Shutdown // Power off
376 };
377
378 PowerManagementUnit(const std::string& name);
379
380 // Power domains
381 void addPowerDomain(const std::string& domain, double voltage, double current);
382 void removePowerDomain(const std::string& domain);
383
384 // Voltage regulation
385 double getVoltage(const std::string& domain) const;
386 void setVoltage(const std::string& domain, double voltage);
387
388 // Current monitoring
389 double getCurrent(const std::string& domain) const;
390 double getTotalPower() const;
391
392 // Power states
393 PowerState getPowerState() const { return power_state_; }
395
396 // Dynamic voltage and frequency scaling
397 void enableDVFS(bool enable) { dvfs_enabled_ = enable; }
398 bool isDVFSEnabled() const { return dvfs_enabled_; }
399
400 // Simulation
401 void simulate(double time_step) override;
402 std::string getDescription() const override;
403
404private:
405 struct PowerDomain {
406 double voltage; // V
407 double current; // A
408 bool is_enabled;
409 };
410
411 std::map<std::string, PowerDomain> power_domains_;
412 PowerState power_state_;
413 bool dvfs_enabled_;
414
415 void updatePowerMetrics();
416};
417
421class SoC : public Component {
422public:
423 SoC(const std::string& name, const std::string& part_number);
424
425 // Core components
426 void addProcessorCore(std::shared_ptr<ProcessorCore> core);
427 void addMemoryController(std::shared_ptr<MemoryController> controller);
428 void addGPUCore(std::shared_ptr<GPUCore> gpu);
429 void addDSPCore(std::shared_ptr<DSPCore> dsp);
430 void addInterface(std::shared_ptr<CommunicationInterface> interface);
431 void addPMU(std::shared_ptr<PowerManagementUnit> pmu);
432
433 // Configuration
434 const std::string& getPartNumber() const { return part_number_; }
435
436 // Performance analysis
437 double getTotalPower() const;
438 double getMaxPerformance() const;
439 std::vector<std::string> getCriticalPaths() const;
440
441 // Hierarchical optimization
443 double calculateTotalArea() const override;
444 size_t getTotalGateCount() const override;
445
446 // Simulation
447 void simulate(double time_step) override;
448 std::string getDescription() const override;
449
450private:
451 std::string part_number_;
452
453 std::vector<std::shared_ptr<ProcessorCore>> processor_cores_;
454 std::vector<std::shared_ptr<MemoryController>> memory_controllers_;
455 std::vector<std::shared_ptr<GPUCore>> gpu_cores_;
456 std::vector<std::shared_ptr<DSPCore>> dsp_cores_;
457 std::vector<std::shared_ptr<CommunicationInterface>> interfaces_;
458 std::vector<std::shared_ptr<PowerManagementUnit>> pmus_;
459
460 void analyzeInterconnect();
461 void optimizeFloorplan();
462};
463
468public:
469 // Processor cores
470 static std::shared_ptr<ProcessorCore> createCortexA53(const std::string& name, size_t cores = 4);
471 static std::shared_ptr<ProcessorCore> createCortexA72(const std::string& name, size_t cores = 4);
472 static std::shared_ptr<ProcessorCore> createCortexA78(const std::string& name, size_t cores = 4);
473 static std::shared_ptr<ProcessorCore> createCortexM4(const std::string& name);
474 static std::shared_ptr<ProcessorCore> createCortexM7(const std::string& name);
475 static std::shared_ptr<ProcessorCore> createRISCVCore(const std::string& name, CPUArchitecture arch);
476
477 // Memory controllers
478 static std::shared_ptr<MemoryController> createDDR4Controller(const std::string& name, size_t channels = 2);
479 static std::shared_ptr<MemoryController> createDDR5Controller(const std::string& name, size_t channels = 2);
480 static std::shared_ptr<MemoryController> createLPDDR5Controller(const std::string& name, size_t channels = 4);
481
482 // GPU cores
483 static std::shared_ptr<GPUCore> createMaliG78(const std::string& name, size_t compute_units = 16);
484 static std::shared_ptr<GPUCore> createAdreno640(const std::string& name);
485 static std::shared_ptr<GPUCore> createAdreno730(const std::string& name);
486
487 // DSP cores
488 static std::shared_ptr<DSPCore> createHexagonDSP(const std::string& name);
489 static std::shared_ptr<DSPCore> createTIC6000(const std::string& name);
490
491 // Communication interfaces
492 static std::shared_ptr<CommunicationInterface> createUSB3Interface(const std::string& name);
493 static std::shared_ptr<CommunicationInterface> createPCIe4Interface(const std::string& name);
494 static std::shared_ptr<CommunicationInterface> createEthernetInterface(const std::string& name);
495
496 // Complete SoCs
497 static std::shared_ptr<SoC> createSnapdragon8Gen1(const std::string& name);
498 static std::shared_ptr<SoC> createAppleM1(const std::string& name);
499 static std::shared_ptr<SoC> createExynos2200(const std::string& name);
500 static std::shared_ptr<SoC> createMediaTekDimensity9000(const std::string& name);
501
502 // Register all IP blocks in library
504};
505
510
514 std::shared_ptr<Component> createCPUDesign(const std::string& name, size_t core_count = 4);
515
519 std::shared_ptr<Component> createMemorySubsystem(const std::string& name);
520
524 std::shared_ptr<Component> createGPUDesign(const std::string& name);
525
529 std::shared_ptr<Component> createCommunicationSubsystem(const std::string& name);
530
534 std::shared_ptr<Component> createSmartphoneSoC(const std::string& name);
535
539 std::shared_ptr<Component> createServerProcessor(const std::string& name);
540
544 std::shared_ptr<Component> createIoTMicrocontroller(const std::string& name);
545}
546
547} // namespace components
548} // namespace zlayout
std::string getDescription() const override
void simulate(double time_step) override
void setProtocolParameter(const std::string &param, const std::string &value)
CommunicationInterface(const std::string &name, InterfaceType type)
std::string getProtocolParameter(const std::string &param) const
Component(const std::string &name, ComponentCategory category)
Component library for managing component definitions.
std::string getDescription() const override
DSPCore(const std::string &name, DSPArchitecture arch)
void setFFTUnit(bool has_fft)
void simulate(double time_step) override
DSPArchitecture getArchitecture() const
void setMACUnits(size_t units)
void setGMACS(double gmacs)
void setViterbiUnit(bool has_viterbi)
void setMaxFrequency(double freq)
void setGFLOPS(double gflops)
std::string getDescription() const override
void setShaderCores(size_t cores)
void setMaxFrequency(double freq)
void simulate(double time_step) override
void setMemoryBusWidth(size_t width)
GPUArchitecture getArchitecture() const
double getMemoryBandwidth() const
void setTexelFillRate(double rate)
double getTexelFillRate() const
GPUCore(const std::string &name, GPUArchitecture arch, size_t compute_units=8)
size_t getMemoryBusWidth() const
void setMemoryBandwidth(double bandwidth)
Standard IP Block Factory.
static std::shared_ptr< SoC > createAppleM1(const std::string &name)
static std::shared_ptr< GPUCore > createAdreno640(const std::string &name)
static std::shared_ptr< ProcessorCore > createRISCVCore(const std::string &name, CPUArchitecture arch)
static std::shared_ptr< MemoryController > createDDR4Controller(const std::string &name, size_t channels=2)
static void registerStandardIPBlocks(ComponentLibrary &library)
static std::shared_ptr< CommunicationInterface > createUSB3Interface(const std::string &name)
static std::shared_ptr< SoC > createMediaTekDimensity9000(const std::string &name)
static std::shared_ptr< ProcessorCore > createCortexA78(const std::string &name, size_t cores=4)
static std::shared_ptr< CommunicationInterface > createEthernetInterface(const std::string &name)
static std::shared_ptr< ProcessorCore > createCortexA72(const std::string &name, size_t cores=4)
static std::shared_ptr< ProcessorCore > createCortexM4(const std::string &name)
static std::shared_ptr< SoC > createSnapdragon8Gen1(const std::string &name)
static std::shared_ptr< DSPCore > createTIC6000(const std::string &name)
static std::shared_ptr< SoC > createExynos2200(const std::string &name)
static std::shared_ptr< CommunicationInterface > createPCIe4Interface(const std::string &name)
static std::shared_ptr< MemoryController > createLPDDR5Controller(const std::string &name, size_t channels=4)
static std::shared_ptr< ProcessorCore > createCortexA53(const std::string &name, size_t cores=4)
static std::shared_ptr< DSPCore > createHexagonDSP(const std::string &name)
static std::shared_ptr< MemoryController > createDDR5Controller(const std::string &name, size_t channels=2)
static std::shared_ptr< ProcessorCore > createCortexM7(const std::string &name)
static std::shared_ptr< GPUCore > createAdreno730(const std::string &name)
static std::shared_ptr< GPUCore > createMaliG78(const std::string &name, size_t compute_units=16)
void setTimingParams(const TimingParams &params)
void setCapacityPerChannel(size_t capacity)
MemoryController(const std::string &name, MemoryType type, size_t channels=1)
std::string getDescription() const override
const TimingParams & getTimingParams() const
void simulate(double time_step) override
std::string getDescription() const override
void removePowerDomain(const std::string &domain)
double getVoltage(const std::string &domain) const
void setVoltage(const std::string &domain, double voltage)
void simulate(double time_step) override
void addPowerDomain(const std::string &domain, double voltage, double current)
double getCurrent(const std::string &domain) const
PowerManagementUnit(const std::string &name)
void setL2Config(const CacheConfig &config)
Definition ip_blocks.hpp:91
void setL1Config(const CacheConfig &config)
Definition ip_blocks.hpp:90
void setPipelineStages(size_t stages)
const CacheConfig & getL1Config() const
Definition ip_blocks.hpp:94
const CacheConfig & getL3Config() const
Definition ip_blocks.hpp:96
const CacheConfig & getL2Config() const
Definition ip_blocks.hpp:95
void setCurrentFrequency(double freq)
Definition ip_blocks.hpp:79
void simulate(double time_step) override
std::string getDescription() const override
CPUArchitecture getArchitecture() const
Definition ip_blocks.hpp:71
ProcessorCore(const std::string &name, CPUArchitecture arch, size_t core_count=1)
void setVectorUnit(bool has_vector)
void setL3Config(const CacheConfig &config)
Definition ip_blocks.hpp:92
void setFloatingPoint(bool has_fpu)
void addMemoryController(std::shared_ptr< MemoryController > controller)
geometry::Rectangle calculateHierarchicalBoundingBox() const override
void addProcessorCore(std::shared_ptr< ProcessorCore > core)
double calculateTotalArea() const override
size_t getTotalGateCount() const override
std::vector< std::string > getCriticalPaths() const
void addGPUCore(std::shared_ptr< GPUCore > gpu)
std::string getDescription() const override
SoC(const std::string &name, const std::string &part_number)
double getTotalPower() const
double getMaxPerformance() const
const std::string & getPartNumber() const
void addDSPCore(std::shared_ptr< DSPCore > dsp)
void addPMU(std::shared_ptr< PowerManagementUnit > pmu)
void simulate(double time_step) override
void addInterface(std::shared_ptr< CommunicationInterface > interface)
Axis-aligned rectangle for bounding boxes and simple EDA components.
Definition rectangle.hpp:26
Hierarchical EDA Component System.
Digital Logic Circuit Components.
std::shared_ptr< SoC > createSmartphoneSoC()
Create a complete SoC with multiple IP blocks.
Real-world circuit examples for timing optimization.
std::shared_ptr< Component > createGPUDesign(const std::string &name)
Create a graphics processing unit with compute pipelines.
std::shared_ptr< Component > createServerProcessor(const std::string &name)
Create a server processor with multiple cores.
std::shared_ptr< Component > createCPUDesign(const std::string &name, size_t core_count=4)
Create a realistic CPU design with proper timing constraints.
std::shared_ptr< Component > createIoTMicrocontroller(const std::string &name)
Create an IoT microcontroller design.
std::shared_ptr< Component > createMemorySubsystem(const std::string &name)
Create a memory subsystem with realistic timing.
std::shared_ptr< Component > createCommunicationSubsystem(const std::string &name)
Create a communication subsystem with multiple interfaces.
CPUArchitecture
CPU Architecture types.
Definition ip_blocks.hpp:24
InterfaceType
Communication interface types.
Definition ip_blocks.hpp:50
MemoryHierarchy
Memory hierarchy types.
Definition ip_blocks.hpp:39
Main namespace for ZLayout library.
Definition component.hpp:20